| PART |
Description |
Maker |
| MSK4890H MSK4890 MSK4890E |
600V/300A SCR/REGEN PEM
|
MSK[M.S. Kennedy Corporation]
|
| IDT5T9050PGI IDT5T9050 |
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFERJR 2.5V的单数据传输速率1:5时钟缓冲器TERABUFFER⑩JR
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER⑩ JR
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer Jr.
|
Integrated Device Technology, Inc.
IDT[Integrated Device Technology]
|
| W631GG6KB-15 W631GG6KB12A W631GG6KB12I W631GG6KB12 |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| M14D5121632A-2K |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
| M14D2561616A-2E |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
| SH713609 SH7137 |
SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer
|
Renesas Electronics Corporation
|
| NB6L572M NB6L572MMNG NB6L572MMNR4G |
6L SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32
2.5V / 3.3V Differential 4:1 Mux to 1:2 CML Clock/Data Fanout / Translator
2.5V / 3.3V Differential 4:1 Mux to 1:2 CML Clock/Data Fanout / Translator
|
ON Semiconductor
|
| W9412G2IB W9412G2IB4 W9412G2IB-6I |
1M × 4 BANKS × 32 BITS GDDR SDRAM
Double Data Rate architecture; two data transfers per clock cycle
4M X 32 DDR DRAM, 0.7 ns, PBGA144
|
Winbond
WINBOND ELECTRONICS CORP
|
| SY87700LHG SY87700LZG SY87700LHGTR |
3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY CLOCK RECOVERY CIRCUIT, PDSO28
3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY CLOCK RECOVERY CIRCUIT, PQFP32
|
Micrel Semiconductor,Inc.
Micrel Semiconductor, Inc.
|
| SY58019UMG SY58019UMG-TR |
Clock and Timing - Clock and Data Distribution
|
Microchip
|
